Quadrature Encoders The image below shows the disk for a quadrature encoder. This device creates a series of pulse strings when a shaft rotates, and is used to measure angle or speed of a shaft.

ELEC2042 2020 Session 2
Assignment 2 (Version 2)
Due: Friday 23rd October 2020
Quadrature Encoders
The image below shows the disk for a quadrature encoder. This device creates a series of pulse strings when a shaft rotates, and is used to measure angle or speed of a shaft.
There are two rings of alternating back and white areas. The inner ring is the ‘A’ ring, and the outer ring is the ‘B’ ring. Each ring has a sensor that returns a ‘1’ when faced with white, and a ‘0’ when faced with back. These sensors output two pulse trains, normally called ‘A’ and ‘B’ as per the ring. They are offset, and depending on whether the shaft is turning clockwise or anti-clockwise the A channel rising edge will lead or trail the B channel rising edge.
There is a third ring with an index pulse. You do not need to consider this ring for this assignment.
You are to design a circuit, and produce the Sum of Products (SoP) terms for that circuit, to create a counter that allows us to determine where the shaft is currently located. You need to explain how your circuit works, and why you selected the SoP in your solution.
There are several parts to this assignment. For a Pass mark your counter must give an accurate position count, incrementing or decrementing as the shaft is rotated. For a Credit or Distinction mark you need to add in timing information for your circuit and calculate what is the maximum speed at which the shaft can rotate for your circuit. For a High Distinction mark you circuit must capture very high precision information about the shaft’s rotation, and must be completely self clocking, along with the associated timing information.
It is expected that an average student will spend 5 hours to achieve a P mark on this assignment, and 20 hours for a HD mark.
Your submission MUST be fully typeset. No handwritten/scanned work will be accepted. Submission must be made through Turnitin. Turnitin will require the text of the submission to be machine scanable.
All SoP equations must be clear and easily legible.
Part 1 (50%):
You have a quadrature encoder connected to a shaft. The waveforms for that encoder are shown below for both clockwise and counter-clockwise rotation. The design states that clockwise rotation will cause the -position- to increase, and counter clockwise rotation will cause the -position- to decrease.
The encoder produces 18 pulses per revolution from each of the A and B channels. Each pulse would be a 50% duty cycle is the encoder is rotating at a constant angular velocity. The pulses vary in duration depending on the encoder’s velocity.
Clockwise rotation of the encoder:

The inputs to your circuit are A, B and RESET. The outputs are POSN0 to POSN7, a signed twos complement number with POSN0 the least significant bit, and POSN7 the most significant bit. These outputs are always enabled.
Using the A signal as the clock for your circuit. use the B signal and the current position count to determine the new position count.
Design a circuit using the three specified inputs; A, B and RESET. The A input should be used as your clock signal. You need to create any Karnaugh maps required, and eventually write out SoP equations. Show your working for the SoP equations for the position counter. The equations do not have to be minimal as the non-optimality increases readability.
HINT: You can create either an up/down counter directly, or you can have a register interconnected with a full adder. One of these is a better solution.
You are limited to a maximum of 8 inputs on a NAND gate.
Part 2 (30%):
Following from Part 1:
Assuming the following timings:
A D flip flop clock rising edge to Q output valid, minimum 35ns
A D flip flop D input valid BEFORE clock rising edge, minimum 15ns
A NAND gate, or inverter, any number of inputs, change of input to output, minimum 10ns
Calculate the minimum time required to process the quadrature signals, and hence the minimum time between clock pulses.
Calculate the maximum RPM that the encoder can turn so that the pulses do not breech the minimum time requirements.
Part 3 (20%): (This part is hard)
The above parts only increment or decrement the position count on the rising edge of the A signal.
We can do better than this. We want to use both the rising and the falling edge of both the A and the B signals to clock our circuit. This will give us four times the resolution for the counter, boosting it to 72 positions per revolution.
HINT: Review how a D flip flop works internally.
Also, because we have more pulses per revolution we want to increase our position count to 16 bits.
Finally, minimise the time taken for the counter through the use of look ahead techniques we have talked about in class.
Design a circuit that updates the position count on either the rising or falling edge of both A and B signals.
Draw a schematic diagram of the circuit, and create the SoP equations for the circuit.
Calculate the timings and show the critical path.
What is the maximum speed (in RPM) that the encoder can turn so that the pulses do not breech the minimum time requirements.
Submittables:
For Part 1 you need to include in your submission:
1. A schematic for your circuit,
2. The truth table for any state machines in your circuit,
3. Karnaugh Maps for each output in your truth table,
4. The SoP (not necessarily minimum) for your Karnaugh Maps, and
5. A written description of your circuit, how it works and if your Karnaugh Maps are non optimal, why you selected the SoP equations you did.
For Part 2 you need to include in your submission:
1. The timing calculations from your circuit, showing intermediate values along the critical path,
2. The minimum time required from a clock pulse until another clock pulse will correctly capture the next state,
3. The maximum frequency at which your circuit can operate, and
4. From the frequence the maximum RPM the shaft can turn to ensure the clocking rules are not violated.
5. A written explanation of your timing, frequency and ratational speed calculations.
For Part 3 you need to include in your submission:
1. A schematic for your circuit,
2. The truth table for any state machines in your circuit,
3. Karnaugh Maps for each output in your truth table,
4. The SoP (not necessarily minimum) for your Karnaugh Maps,
5. The timing calculations from your circuit, showing intermediate values along the critical path,
6. The minimum time required from a clock pulse until another clock pulse will correctly capture the next state,
7. The maximum frequency at which your circuit can operate, and
8. From the frequence the maximum RPM the shaft can turn to ensure the clocking rules are not violated.
9. A written description of your circuit, how it works and if your Karnaugh Maps are non optimal, why you selected the SoP equations you did, as well as a description of your timing, frequency and ratational speed calculations.